The art is replete with multiplexing circuits which employ various types of gating networks to implement the multiplex function. Some circuits employ a cascode series connection of a pair of transistors to provide the switching function. This arrangement requires a larger supply voltage to accommodate voltage shifts which occur through the circuit. In addition, additional circuit features are needed to move the logic levels back within desired limits.
To implement high speed multiplexer functions, bipolar transistors offer the highest speed switching action. In bipolar circuits, however, care must be taken to avoid saturation effects, both in devices which act as gates and devices which accomplish controlled switching of the signals. Furthermore, substantial design efforts are required to minimize silicon real estate devoted to the multiplexing function.
Other types of switching networks are shown in the prior art. In U.S. Pat. Nos. 2,535,303 to Lewis, 2,576,026 to Meacham, and 2,657,318 to Rack, three-diode, T network switches are shown which are connected in a common cathode arrangement. The switching potential is applied to the anode of one diode to cause it to conduct and to attenuate signal transfer between the other two diodes. Such switching circuits are shown implemented in a multiplexer arrangements.
In U.S. Pat. No. 2,906,869 to Kramskoy, an early style multiplexer circuit is shown wherein diode tubes provide inputs to a triode gate. In U.S. Pat. No. 2,913,528 to DenHertog et al., a scanning by provision of a shunt diode having a gating potential applied to its cathode. By using the gating potential to change the conductivity state of the diode, the conductivity state of a series connected gate diode is thereby controlled. In U.S. Pat. No. 3,029,310 to Heiser, a frequency scanned switching circuit is shown which also employs a diode clamp on a signal line as a gating device.
In U.S. Pat. No. 3,096,447 to Hill et al., a switching circuit is shown having gates which are biased by a signal being gated. The Hill et al. switching circuit is controlled by conduction level of a collector-emitter path of a shunt connected transistor.
In U.S. Pat. No. 4,390,988 to Best et al., a multiplexer is shown which employs a plurality of gated field effect transistors as input gates to a many-two-one multiplexing circuit. In U.S. Pat. No. 4,461,960 to Yasunaga, a multiplexing circuit is shown which employs a shunt connected transistor for clamping the base input of a switching stage. In U.S. Pat. No. 4,551,634 to Takahashi et al., an MOS multiplexing circuit is described wherein a shunt MOS device is employed to clamp a connection point between first and second MOS switching transistors.
Accordingly, it is an object of this invention to provide a high speed multiplexing circuit which uses minimum semiconductor real estate.
It is another object of this invention to provide a high speed multiplexing circuit which employs bipolar, emitter coupled logic technology.
It is still another object of this invention to provide a bipolar emitter coupled logic multiplexing circuit whose functioning is controlled by either a multiplexing switch or a decoder circuit.